View ISL5988507_4138738.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL59885
Data Sheet August 15, 2007 FN7442.6
Auto-Adjusting Sync Separator for HD and SD Video
The ISL59885 video sync separator extracts sync timing information from both standard and non-standard video inputs in the presence of Macrovision pulses. The ISL59885 provides horizontal, vertical, and composite sync outputs as well as SD/HDTV detection. An auto input frequency detect feature automatically adapts to a wide range of video standards (it does not need a different RSET resistor for different frequencies). The vertical sync pulse is output on the rising edge of the first vertical serration following the vertical pre-equalizing string. For non-standard vertical inputs, a default vertical pulse is output when the vertical signal stays low for longer than the vertical sync default delay time. The horizontal output gives horizontal timing with pre/post equalizing pulses. Fixed 70mV sync tip slicing provides sync edge detection when the video input level is between 0.5VP-P and 2VP-P. The ISL59885 is available in an 8 Ld SOIC package and is specified for operation over the full -40C to +85C temperature range.
Features
* NTSC, PAL, SECAM, HDTV, non-standard video sync separation * Fixed 70mV slicing of video input levels from 0.5VP-P to 2VP-P * Single 3V to 5V supply * Composite sync output * Vertical output * Horizontal output * HDTV detection * Macrovision compatible * Available in 8 Ld SOIC package * Pb-free available (RoHS compliant)
Applications
* High definition video equipment
Demo Board
* A dedicated demo board is available
Pinout
ISL59885 (8 LD SOIC) TOP VIEW
COMPOSITE SYNC OUT 1 COMPOSITE VIDEO IN 2 VERTICAL SYNC OUT 3 GND 4 8 VDD 7 HORIZONTAL OUTPUT 6 CSET 5 HD
Ordering Information
PART NUMBER ISL59885IS* ISL59885ISZ* (Note) PART MARKING 59885 IS 59885 ISZ PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG. # MDP0027 MDP0027
*Add "-T7" or "-T13" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59885
Absolute Maximum Ratings (TA = +25C)
VDD Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Operating Ambient Temperature Range . . . . . . . . . .-40C to +85C
Thermal Information
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
DC Electrical Specifications
PARAMETER IDD, Quiescent Clamp Voltage Clamp Discharge Current Clamp Charge Current VOL Output Low Voltage VOH Output High Voltage
VDD = 3.3V, TA = +25C, CSET = 56nF, unless otherwise specified. DESCRIPTION VDD = 3.3V Pin 2, ILOAD = -100A Pin 2 = 2V Pin 2 = 1V IOL = 1.6mA IOH = -40A IOH = -1.6mA 3 2.5 MIN (Note 1) 1.5 1.35 6 -9 TYP 2.2 1.5 15 -7.2 0.24 3.2 3.0 MAX (Note 1) 4 1.65 30 -5.2 0.5 UNIT mA V A mA V V V
Dynamic Characteristics
PARAMETER Comp Sync Prop Delay, tCS Horizontal Sync Delay, tHS Horizontal Sync Width, tHS-PW Vertical Sync Width, tVS Vertical Sync Default Delay, tVSD Input Dynamic Range Slice Level HD Pin Level NOTE: 1. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. DESCRIPTION (See Figure 9) (See Figure 9) (See Figure 9) Normal or default trigger, 50% to 50% (see Figure 7) (See Figure 10) Video input amplitude to maintain slice level spec, VDD = 3.3V VSLICE above VCLAMP 720p, 1080i, 1080p 3.8 230 28 0.5 50 70 0 MIN (Note 1) TYP 35 40 5.2 280 50 MAX (Note 1) 75 80 6.2 350 68 2 90 UNIT ns ns s s s VP-P mV V
2
FN7442.6 August 15, 2007
ISL59885 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME PIN FUNCTION Composite Sync Out Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge. Composite Video In AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase). Vertical Sync Out Gnd HD CSET Horizontal Output VDD Vertical sync pulse output; the falling edge of vertical sync is the start of the vertical period. Supply ground Low when input horizontal frequency is greater than 20kHz. (An external capacitor to ground); bypass pin for internal bias generator. Horizontal output; falling edge active Positive supply
Typical Performance Curves
VDD = 3.3 AND 5.0V HSYNC PULSEWIDTH (ns)
VDD = 3.3 AND 5.0V
VCSET (V)
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
HSYNC (Hz)
HSYNC FREQUENCY (Hz)
FIGURE 1. HSYNC vs VCSET (RSET = OPEN)
FIGURE 2. HSYNC PULSEWIDTH vs HSYNC FREQUENCY (RSET = OPEN)
VDD = 3.3 AND 5.0V HSYNC BLANKING TIME (s) 0.5V/DIV 5V/DIV 5V/DIV VIN HSYNC VSYNC
5V/DIV
CSYNC
100s/DIV VCSET (V)
FIGURE 3. HSYNC vs VCSET (RSET = OPEN)
FIGURE 4. MACROVISION COMPATIBILITY (NTSC)
3
FN7442.6 August 15, 2007
ISL59885 Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.8 1.6 POWER DISSIPATION (W) 1.4 1.2 1.136W 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 TEMPERATURE (C) 0 0 25 50 75 85 100 125 150 TEMPERATURE (C)
J OI C A= +1 8 S
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 POWER DISSIPATION (W) 1.0 0.8 0.6 0.4 0.2 781mW
J SO
10 C /W
IC A= 8 +1 6 0
C/ W
FIGURE 5. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE 1.5s 0.1s TIME VERTICAL BLANKING INTERVAL = 20H 3H 1 2 3 4 3H 5 6 7 3H 8 9 10 19 20 21
+63.5s +H 1271s -0s -H
H SYNC INTERVAL H
START OF H FIELD ONE PREEQUALIZING PULSE INTERVAL
H VERTICAL SYNC PULSE INTERVAL 9 LINE VERTICAL INTERVAL
0.5H POSTEQUALIZING PULSE INTERVAL
H
REF SUBCARRIER PHASE, COLOR FIELD ONE
SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1
SIGNAL 1c. VERTICAL SYNC OUTPUT, PIN 3
tVS SIGNAL 1d. HORIZONTAL SYNC OUTPUT, PIN 7
NOTES: 2. The composite sync output reproduces all the video input sync pulses, with a propagation delay. 3. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge with a propagation delay. 4. Horizontal sync output produces the true "H" pulses of nominal width of 5s. It has the same delay as the composite sync. FIGURE 7. TIMING DIAGRAM
4
FN7442.6 August 15, 2007
ISL59885
CONDITIONS: VDD = 3.3V/5V, TA = +25C
COLOR BURST INPUT DYNAMIC RANGE 0.5V TO 2V SYNC IN VSLICE 50% VSYNC (SYNC TIP VOLTAGE) SYNC LEVEL
WHITE LEVEL VIDEO
VBLANK (BLANKING LEVEL VOLTAGE)
SYNC
SYNC TIP tdSYNCOUT
DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL SYNC OUT
tdHOUT HOUT
tHOUT
FIGURE 8. HORIZONTAL INTERVAL 525/625 LINE COMPOSITE TYP (Note 5) 65 470 5.2
PARAMETER tdSYNCOUT tdHOUT tHOUT NOTE:
DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input Horizontal Output Width (See Figure 8) (See Figure 8) (See Figure 8)
CONDITIONS
UNIT ns ns s
5. Delay variation is less than 2.5ns over-temperature range.
5
FN7442.6 August 15, 2007
ISL59885
SIGNAL 2a. COMPOSITE VIDEO INPUT 70mV
SLICE LEVEL
tCS COMP SYNC PROP DELAY SIGNAL 2b. COMPOSITE SYNC OUTPUT
SIGNAL 2c. VERTICAL SYNC OUTPUT
tCS-VS COMP SYNC VERT SYNC DELAY
SIGNAL 2d. HORIZONTAL SYNC OUTPUT
tHS tHS-PW
FIGURE 9. STANDARD VERTICAL TIMING
LINES 2 SIGNAL 3a. COMPOSITE VIDEO INPUT 3 4 5
(NO VERTICAL SYNC PULSES)
tVSD SIGNAL 3b. VERTICAL SYNC OUTPUT
VERT SYNC DEFAULT DELAY
FIGURE 10. NON-STANDARD VERTICAL TIMING
6
FN7442.6 August 15, 2007
ISL59885
COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE START OF FIELD ONE
622
623
624
625
1
2
3
4
5
6
7
23
24
SYNCOUT OUTPUT
VOUT OUTPUT
tVS
HOUT OUTPUT
NOTES: 6. The composite sync output reproduces all the video input sync pulses, with a propagation delay. 7. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
FIGURE 11. EXAMPLE OF VERTICAL INTERVAL (625)
SYNCIN 1123 SYNCOUT 1124 1125 1 2 3 4 5 6 7 8 ... 21
HOUT
VOUT
SYNCIN 560 SYNCOUT 561 562 563 564 565 566 567 568 569 570 ... 583
HOUT
VOUT
FIGURE 12. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED
7
FN7442.6 August 15, 2007
ISL59885
SYNCIN 1245 SYNCOUT 1246 1247 1248 1249 1250 1 2 3 4 5 ... 48
HOUT
VOUT
SYNCIN 620 SYNCOUT 621 622 623 624 625 626 627 628 629 630 ... 673
HOUT VOUT
FIGURE 13. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED (1250 LINES)
8
FN7442.6 August 15, 2007
ISL59885
CONDITIONS: VDD = 3.3V/5V, TA = +25C
SYNCIN
tdSYNCOUT SYNC OUT
tdHOUT HOUT
tHOUT
FIGURE 14. HORIZONTAL INTERVAL (HDTV) (720p)
H Timing for HDTV, No Filter (using 720p input signal)
PARAMETER tdSYNCOUT tdHOUT tHOUT NOTE: 8. Delay variation is less than 2.5ns over-temperature range. DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input Horizontal Output Width (See Figure 14) (See Figure 14) (See Figure 14) CONDITIONS TYP TYP @ 5V @ 3.3V (Note 8) (Note 8) 56 48 1.90 50 36 1.90 UNIT ns ns s
9
FN7442.6 August 15, 2007
ISL59885
CONDITIONS: VDD = 3.3V/5V, TA = +25C
SYNCIN
tdSYNCOUT SYNC OUT
tdHOUT HOUT
tHOUT
FIGURE 15. HORIZONTAL INTERVAL (HDTV) (720p)
H Timing for HDTV, With Filter (using 720p input)
PARAMETER tdSYNCOUT tdHOUT tHOUT NOTE: 9. Delay variation is less than 2.5ns over-temperature range. DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input Horizontal Output Width (See Figure 15) (See Figure 15) (See Figure 15) CONDITIONS TYP TYP @ 5V @ 3.3V (Note 9) (Note 9) 120 112 200 110 100 200 UNIT ns ns ns
10
FN7442.6 August 15, 2007
ISL59885 Applications Information
Video In
The "Simplified Block Diagram" is shown on page 12. An AC coupled video signal is input to Video In pin 2 via C1, nominally 0.1F. Clamp charge current will prevent the signal on pin 2 from going any more negative than Sync Tip Ref, about 1.5V. This charge current is nominally about 1mA. A clamp discharge current of about 10A is always attempting to discharge C1 to Sync Tip Ref, thus charge is lost between sync pulses that must be replaced during sync pulses. The droop voltage that will occur can be calculated from IT = CV, where V is the droop voltage, I is the discharge current, t is the time between sync pulses (sync period sync tip width), and C is C1. An NTSC video signal has a horizontal frequency of 15.73kHz, and a sync tip width of 4.7s. This gives a period of 63.6s and a time t = 58.9s. The droop voltage will then be V = 5.9mV. This is less than 2% of a nominal sync tip amplitude of 286mV. The charge represented by this droop is replaced in a time given by t = CV/I, where I = clamp charge current = 5.3mA. Here t = 590ns, about 12% of the sync pulse width of 4.7s. It is important to choose C1 large enough so that the droop voltage does not approach the switching threshold of the internal comparator. present on the I/P signal after the true H sync will be ignored, thus the horizontal output will not be effected by MacroVision copy protection. When there is a loss of sync, the Horizontal Sync output is held high.
CSET
An external CSET capacitor connected from CSET pin 6 to ground. CSET capacitor should be a X7R grade or better as the Y5U general use capacitors may be too leaky and cause faulty operation. The CSET capacitor should be very close to the CSET pin to reduce possible board leakage. 56nF is recommended. The "CSET Bias Circuit" is shown on page 12. The CSET capacitor rectifies a 5s pulse current and creates a voltage on CSET. The CSET voltage is converted to bias current for HSYNC and VSYNC timing.
Chroma Filter
A chroma filter is suggested to increase the S/N ratio of the incoming video signal. Use of the optional chroma filter is shown in Figure16. It can be implemented very simply and inexpensively with a series resistor of 100 and a capacitor of 570pF, which gives a single pole roll-off frequency of about 2.79MHz during NTSC or PAL. This sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet passes the approximately 15kHz sync signals without appreciable attenuation. During HDTV, the transistor turns off and a 100pF capacitor is left to filter any noise present at the input. A chroma filter will increase the propagation delay from the composite input to the outputs.
CHROMA FILTER 0.1F ISL59885 1 CSYNC VDD 2 100 3 VSYNC CSET CF 100pF CF2 470pF 4 GND HD 6 5 CVIN HOUT 8 7
Composite Sync
The Composite Sync output is simply a reproduction of the input signal with the active video removed. The sync tip of the Composite video signal is clamped to 1.5V at pin 2 and then slices at 70mV above the sync tip reference. The output signal is buffered out to pin 1. When loss of sync, the Composite Sync output is held low.
VIDEO IN
RF
Vertical Sync
A low-going Vertical Sync pulse is output during the start of the vertical cycle of the incoming video signal. The vertical cycle starts with a pre-equalizing phase of pulses with a duty cycle of about 93%, followed by a vertical serration phase that has a duty cycle of about 15%. Vertical Sync is clocked out of the ISL59885 on the first rising edge during the vertical serration phase. In the absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 60s after the last falling edge of the vertical equalizing phase.
10k MMBT3904
FIGURE 16. OPTIONAL CHROMA FILTER
HD-Detect
High definition video is flagged by HD going low when the input horizontal frequency is greater than 20kHz.
Horizontal Sync
The horizontal circuit senses the composite sync edges and produces the true horizontal pulses of nominal width 5.2s. The leading edge is triggered from the leading edge of the input H sync with the same propagation delay as composite sync. The half line pulses present in the input signal during vertical blanking are removed with an internal 2H line eliminator circuit. This is a circuit that inhibits horizontal output pulses until 75% of the line time is reached, then the horizontal output operation is enabled again. Any signals 11
FN7442.6 August 15, 2007
ISL59885 Simplified Block Diagram
CLAMP SYNC TIP REF 1.5V COMPOSITE VIDEO IN 2 SLICE 1.57V GND 4 CSET C3 56nF HD DETECTOR 5 HD VDD 8 VDD 5V C2 0.1F COMP. + 1 COMPOSITE SYNC
RF 620 CF 510pF
C1 0.1F
6
REF GEN
SYNC TIP 70mV SLICE
V SYNC
3 VERTICAL SYNC OUT
H SYNC
7 HORIZONTAL SYNC OUT
2H ELIMINATOR
CSET Bias Circuit
VDD VDD
CSYNC
PULSE 5s
CSET 56nF
+ IBIAS - TIMING
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN7442.6 August 15, 2007
ISL59885 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
13
FN7442.6 August 15, 2007

▲Up To Search▲

Price & Availability of ISL5988507

	To Download ISL5988507 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .